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L. McLaughlin, Analysis and characterization of BiCMOS for high-speed digital logic, IEEE J. SolidState Circuits, 23: 558–565, 1988. 14. C. Mead and L. Conway, Introduction to VLSI Systems, Reading, MA: Addison-Wesley, 1980. htm }{{}} ● HOME ● ABOUT US ● CONTACT US ● HELP Home / Engineering / Electrical and Electronics Engineering Wiley Encyclopedia of Electrical and Electronics Engineering Bicmos Memory Circuits Standard Article Lee S. , Sunnyvale, CA Copyright © 1999 by John Wiley & Sons, Inc.

Solid-State Circuits, 27 2, Feb. 1992. 3. R. E. Ladner and M. J. Fischer, Parallel prefix computation, J. ACM, 27 (4): 831–838, 1980. 4. B. W. Y. Wei and C. D. Thompson, Area-time optimal adder design, IEEE Trans. , 39 (5): 1990. 5. R. P. Brent and H. T. Kung, A regular layout for parallel adders, IEEE Trans. , 31 (3): 1982. 6. B. W. Y. -F. Chen, QAC: A CMOS implementation of the 32-bit Q adder, Proc. IEEE Int. Conf. Comput. , Port Chester, NY, October 1985. 7. T. F. Ngai, M. J. Irwin, and S. Rawat, Regular, area-time efficient carry-lookahead adders, J.

13(c), actually reduces the number of differential pairs and thus eases the problem of pitch-matching the sense amp to the SRAM cell column (19). Since the bit lines are typically precharged high, the CMOS transmission-gate n-FET is not required. Note that the sense_L inputs are one-low predecoded signals in this case. This technique can be readily modified to have an n-FET current source and/or distributed data lines as in the circuit in Fig. 13(b). Current Sense Amps. An alternative to the familiar voltagebased differential-pair sense amp is a fully-differential current sense amp, such as the one shown in Fig.

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